Introduction - Freescale Semiconductor MCF52277 Reference Manual

Chapter 8
Power Management
8.1

Introduction

This chapter explains the low-power operation of the device.
8.1.1 Features
These features support low-power operation:
• Four operation modes: run, wait, doze, and stop
• Ability to shut down most peripherals independently
• Ability to shut down clocks to most peripherals independently
• Ability to run the device in low-frequency limp mode
• Ability to shut down the external FB_CLK pin
8.2 Memory Map/Register Definition
The power management programming model consists of registers from the SCM and CCM memory space:
Address
0xFC04_0013 Wakeup Control Register (WCR)
0xFC04_002C Peripheral Power Management Set Register (PPMSR)
0xFC04_002D Peripheral Power Management Clear Register (PPMCR)
0xFC04_0030 Peripheral Power Management High Register (PPMHR)
0xFC04_0034 Peripheral Power Management Low Register (PPMLR)
0xFC0A_0007 Low-Power Control Register (LPCR)
0xFC0A_0010 Miscellaneous Control Register (MISCCR)
0xFC0A_0012 Clock Divider Register (CDR)
1
User access to supervisor only address locations have no effect and result in a bus error
2
The MISCCR and CDR registers are described in
Freescale Semiconductor
Table 8-1. Power Management Memory Map
Register
Supervisor Access Only Registers
2
2
Chapter 9, "Chip Configuration Module (CCM)."
MCF52277 Reference Manual, Rev. 1
Width
Access Reset Value
(bits)
1
8 R/W 0x00
8 W 0x00
8 W 0x00
32 R/W 0x0000_0000
32 R/W 0x0000_0000
8 R/W 0x00
16 R/W See Section
16 R/W 0x0001
Section/Page
8.2.1/8-2
8.2.2/8-3
8.2.3/8-4
8.2.4/8-4
8.2.4/8-4
8.2.5/8-7
10.3.5/10-11
10.3.6/10-13
8-1