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Debug Module
The first version 2 ColdFire core devices implemented the original debug architecture, now called revision
A. Based on feedback from customers and third-party developers, enhancements have been added to
succeeding generations of ColdFire cores. For revision A, CSR[HRL] is 0. See
"Configuration/Status Register
Revision B (and B+) of the debug architecture offers more flexibility for configuring the hardware
breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while
hardware breakpoint registers are active. Revision B+ adds three new PC breakpoint registers. For
revision B, CSR[HRL] is 1, and for revision B+, CSR[HRL] is 0x9.
The following table summarizes the various debug revisions.
Revision
CSR[HRL]
A
B
B+
32.2
Signal Descriptions
Table 32-2
describes debug module signals. All ColdFire debug signals are unidirectional and related to a
rising edge of the processor core's clock signal. The standard 26-pin debug connector is shown in
Section 32.8, "Freescale-Recommended BDM
Signal
Development Serial
Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two
Clock (DSCLK)
consecutive rising bus clock edges.) Clocks the serial communication port to the debug module
during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK). At the
synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Development Serial
Internally synchronized input that provides data input for the serial communication port to the debug
Input (DSI)
module after the DSCLK has been seen as high (logic 1).
Development Serial
Provides serial output communication for debug module responses. DSO is registered internally. The
Output (DSO)
output is delayed from the validation of DSCLK high.
Breakpoint (BKPT)
Input requests a manual breakpoint. Assertion of BKPT puts the processor into a halted state after
the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as
the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a
debug interrupt exception in the processor.
32-2
(CSR)".
Table 32-1. Debug Revision Summary
0000
Initial debug revision
0001
BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
_
command to display the processor's current PC
SYNC
PC
1001
3 new PC breakpoint registers PBR1–3
Table 32-2. Debug Module Signals
MCF52277 Reference Manual, Rev. 1
Enhancements
Pinout".
Description
Section 32.4.2,
Freescale Semiconductor
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