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Interrupt Controller Modules
Address
0xFC05_40E0
Global Software Interrupt Acknowledge (GSWIACK)
0xFC05_40E0 + 4n
Global Level n Interrupt Acknowledge Registers
(n=1:7)
(GLnIACK)
15.2.1
Interrupt Pending Registers (IPRHn, IPRLn)
The IPRHn and IPRLn registers,
map for each interrupt request to indicate if there is an active request (1 equals active request, 0 equals no
request) for the given source. The interrupt mask register state does not affect the IPRn. The IPRn is
cleared by reset and is a read-only register, so any attempted write to this register is ignored.
Address 0xFC04_8000 (IPRH0)
0xFC04_C000 (IPRH1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether
INT
an interrupt condition can generate an interrupt. At every system clock, the IPRHn samples the signal generated by
the interrupting source. The corresponding IPRHn bit reflects the state of the interrupt signal even if the
corresponding IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Address 0xFC04_8004 (IPRL0)
0xFC04_C004 (IPRL1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15-4
Table 15-2. Interrupt Controller Memory Map (continued)
Register
Figure 15-1
and
Figure 15-1. Interrupt Pending Register High (IPRHn)
Table 15-3. IPRHn Field Descriptions
Figure 15-2. Interrupt Pending Register Low (IPRLn)
MCF52277 Reference Manual, Rev. 1
Width
Access
(bits)
8
8
Figure
15-2, are each 32 bits in size, and provide a bit
INT
Description
INT
Section/
Reset Value
R
0x00
15.2.10/15-14
R
0x18
15.2.10/15-14
Access: User read-only
8
7
6
5
4
3
2
1
Access: User read-only
8
7
6
5
4
3
2
1
Freescale Semiconductor
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