Freescale Semiconductor MCF52277 Reference Manual page 270

Enhanced Direct Memory Access (eDMA)
• In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal.
All channel priority levels must be unique when fixed arbitration mode is enabled.
• If a scatter/gather operation is enabled upon channel completion, a configuration error is reported
if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration error is reported
when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the
TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report
as the channel activates and asserts an error interrupt request. A scatter/gather configuration error is
reported when the scatter/gather operation begins at major loop completion when properly enabled. A
minor loop channel link configuration error is reported when the link operation is serviced at minor loop
completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA
engine with the current source address, destination address and current iteration count at the point of the
fault. When a system-bus error occurs, the channel terminates after the read or write transaction (which is
already pipelined after errant access) has completed. If a bus error occurs on the last read prior to beginning
the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on
the last write prior to switching to the next read sequence, the read sequence executes before the channel
terminates due to the destination bus error.
The occurrence of any error causes the eDMA engine to stop the active channel immediately, and the
appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error
condition are loaded into the EDMA_ES. The major loop complete indicators, setting the transfer control
descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is
detected. After the error status has been updated, the eDMA engine continues operating by servicing the
next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a
channel is terminated by an error and then issues another service request before the error is fixed, that
channel executes and terminate with the same error condition.
Address: 0xFC04_4004 (EDMA_ES)
31 30
R VLD 0
W
Reset 0 0
15 14
R 0 CPE
W
Reset 0 0
17-6
29 28 27 26
0 0 0 0
0 0 0 0
13 12 11 10
0 0 ERRCHN
0 0 0 0
Figure 17-4. eDMA Error Status Register (EDMA_ES)
MCF52277 Reference Manual, Rev. 1
25 24 23 22
0 0 0 0
0 0 0 0
9 8 7 6
SAE SOE
0 0 0 0
Access: User read-only
21 20 19 18
0 0 0 0
0 0 0 0
5 4 3 2
DAE DOE NCE SGE
0 0 0 0
Freescale Semiconductor
17 16
0 0
0 0
1 0
SBE DBE
0 0