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General Purpose I/O Module
Address: 0xFC0A_4000 (PODR_BE)
0xFC0A_4001 (PODR_CS)
0xFC0A_4002 (PODR_FBCTL)
0xFC0A_4006 (PODR_DSPI)
0xFC0A_4007 (PODR_TIMER)
0xFC0A_4008 (PODR_LCDCTL)
7
R
0
W
Reset:
0
Address: 0xFC0A_4003 (PODR_I2C)
0xFC0A_4009 (PODR_LCDDATAH)
7
R
0
W
Reset:
0
Field
PODR_x Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
Note: See above figures for bit field positions.
14.3.2
Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port pin drivers when the pins are configured for GPIO. The
PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for
all ports are shown in the figures below.
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register
configures the corresponding port pin as an output. Clearing any bit in a PDDR_x register configures the
corresponding pin as an input.
14-12
6
5
0
0
0
0
Figure 14-3. Port x Output Data Registers (PODR_x)
6
5
0
0
0
0
Figure 14-4. Port x Output Data Registers (PODR_x)
Table 14-5. PODR_x Field Descriptions
MCF52277 Reference Manual, Rev. 1
4
3
2
0
0
1
1
4
3
2
0
0
0
0
0
0
Description
Access: User read/write
1
0
PODR_x
1
1
Access: User read/write
1
0
PODR_x
1
1
Freescale Semiconductor
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