Freescale Semiconductor MCF52277 Reference Manual page 428

Universal Serial Bus Interface – On-The-Go Module
20.5.3.6.3 Executing a Transfer Descriptor
To safely add a dTD, the DCD must follow this procedure that manages the event where the device
controller reaches the end of the dTD list. At the same time, a new dTD is added to the end of the list.
Determine whether the linked list is empty:
Check the DCD driver to see if the pipe is empty (internal representation of the linked list should
indicate if any packets are outstanding)
Case 1: Link list is empty
1. Write dQH next pointer AND dQH terminate bit to 0 as a single longword operation.
2. Clear active and halt bit in dQH (in case set from a previous error).
3. Prime endpoint by writing 1 to the correct bit position in the EPPRIME register.
Case 2: Link list is not empty
1. Add dTD to end of the linked list.
2. Read correct prime bit in EPPRIME - if set, DONE.
3. Set the USBCMD[ATDTW] bit.
4. Read correct status bit in EPSR, and store in a temporary variable for later.
5. Read the USBCMD[ATDTW] bit:
If clear, go to 3.
If set, continue to 6.
6. Clear the USBCMD[ATDTW] bit.
7. If status bit read in step 4 is 1 DONE.
8. If status bit read in step 4 is 0 then go to case 1, step 1.
20.5.3.6.4 Transfer Completion
After a dTD is initialized and the associated endpoint is primed, the device controller executes the transfer
upon the host-initiated request. The DCD is notified with a USB interrupt if the interrupt-on-complete bit
was set, or alternatively, the DCD can poll the endpoint complete register to determine when the dTD had
been executed. After a dTD is executed, DCD can check the status bits to determine success or failure.
Multiple dTDs can be completed in a single endpoint complete notification.
After clearing the notification, the DCD must search the dTD linked list and
retire all finished (active bit cleared) dTDs.
By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed
successfully. Success is determined with the following combination of status bits:
• Active = 0, Halted = 0, Transaction error = 0, Data buffer error = 0
Should any combination other than the one shown above exist, the DCD must take proper action. Transfer
failure mechanisms are indicated in
20-70
CAUTION
Section 20.5.3.6.6, "Device Error Matrix."
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor