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Serial Boot Facility (SBF)
2. The system is released from reset.
3. The ColdFire processor initiates its normal reset vector fetch at address 0.
4. The actual memory that responds to the reset vector fetch depends on whether serial boot load is
requested:
— If SBFSR[BLL] is cleared, the reset vector fetch is handled by the FlexBus module and
whatever external memory is mapped at address 0, governed by the user-provided setting of
CCR[FBCONFIG].
— If SBFSR[BLL] is set, the reset vector and boot code are read from the on-chip SRAM. (The
SBF enables the SRAM and maps it to address 0 via the RAMBAR before control of the
processor is restored to the ColdFire core.) The reset vector (initial stack pointer and program
counter) should point to locations in the on-chip SRAM, so that boot code can initialize the
device and load the application software from the SPI memory or via some other mechanism
(e.g. a network server responding to a TFTP client).
10.5
Initialization Information
10.5.1
SPI Memory Initialization
The SBF requires that, prior to device power-up, the SPI memory is loaded with data organized according
to
Table
10-5. See
Chapter 9, "Chip Configuration Module (CCM),"
data definition.
10-6
Table 10-5. SPI Memory Organization
Byte Address
0x0
0x1
0x2
0x3
0x4
0x5
0x6
1
0x7
1
0x8
...
0x6 + 4 × (BLL + 1)
1
1
This assumes SBFSR[BLL] is set. If BLL is cleared, the SBF does
not access data at these addresses.
2
Start of the user code copied into the on-chip SRAM.
MCF52277 Reference Manual, Rev. 1
for the reset configuration (RCON)
Data Contents
{0000,BLDIV[3:0]}
BLL[7:0]
BLL[15:8]
RCON[7:0]
RCON[15:8]
RCON[23:16]
RCON[31:24]
2
CODE_BYTE_0
CODE_BYTE_1
...
CODE_BYTE_[4 × (BLL + 1) - 1]
Freescale Semiconductor
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