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Initial Tx
MBn[RTR]
Code
0
1010
0
1110
23.3.10 Rx Individual Masking Registers (RXIMR0–15)
These registers are used as acceptance masks for received frame IDs if CANMCR[BCC] is set. (If
CANMCR[BCC] is clear, these registers are reserved and do not affect FlexCAN operation.) One mask
register is provided for each message buffer for individual ID masking per MB. The meaning of each mask
bit is the following:
MIn bit = 0: The corresponding incoming ID bit is don't care.
MIn bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
The individual Rx mask registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Also, they can only be accessed by the CPU while the module
is in freeze mode (CANMCR[FRZ, HALT] are set). Out of freeze mode, write accesses are blocked and
read accesses return all zeros. Furthermore, if the CANMCR[BCC] bit cleared, any read or write operation
to these registers results in access error.
These masks are used for standard and extended ID formats.
Address: 0xFC02_0880 (RXIMR0)
0xFC02_0884 (RXIMR1)
...
0xFC02_08B8 (RXIMR14)
0xFC02_08BC (RXIMR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 23-15. FlexCAN Rx Individual Masking Registers (RXIMR0–15)
Freescale Semiconductor
Table 23-13. Message Buffer Code for Tx Buffers (continued)
Code After
Successful
Transmission
1010
1010
MI
Standard ID
MCF52277 Reference Manual, Rev. 1
Description
Transmit a data frame when a remote request frame with the
same ID is received. This message buffer participates
simultaneously in the matching and arbitration processes. The
matching process compares the ID of the incoming remote
request frame with the ID of the MB. If a match occurs, this
message buffer is allowed to participate in the current arbitration
process and the CODE field is automatically updated to 1110 to
allow the MB to participate in future arbitration runs. When the
frame is eventually transmitted successfully, the code
automatically returns to 1010 to restart the process again.
This is an intermediate code automatically written to the
message buffer as a result of match to a remote request frame.
The data frame is transmitted unconditionally once, and then
the code automatically returns to 1010. The CPU can also write
this code with the same effect.
Extended ID
Access: User read/write
8
7
6
5
4
3
2
1
MI
FlexCAN
0
23-21
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