Freescale Semiconductor MCF52277 Reference Manual page 520

FlexCAN
Field
14 Error interrupt mask.
ERRMSK 0 Error interrupt disabled
1 Error interrupt enabled
13 Clock source. Selects the clock source for the CAN interface to be fed to the prescalar. This bit should only be
CLK_SRC changed while the module is disabled.
0 Clock source is EXTAL
1 Clock source is the internal bus clock, f
12 Loop back. Configures FlexCAN to operate in loop-back mode. In this mode, FlexCAN performs an internal loop
LPB back that can be used for self test operation. The bit stream output of the transmitter is fed back internally to the
receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic 1).
FlexCAN behaves as it normally does when transmitting, and treats its own transmitted message as a message
received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame
acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. Transmit
and receive interrupts are generated.
0 Loop back disabled
1 Loop back enabled
11–8 Reserved, must be cleared.
7 Sampling mode. Determines whether the FlexCAN module samples each received bit one time or three times to
SMP determine its value.
0 One sample, taken at the end of phase buffer segment 1, is used to determine the value of the received bit.
1 Three samples are used to determine the value of the received bit. The samples are taken at the normal sample
point and at the two preceding periods of the S-clock; a majority rule is used.
6 Bus off recovery mode. Defines how FlexCAN recovers from bus off state. If this bit is cleared, automatic recovering
BOFFREC from bus off state occurs according to the CAN Specification 2.0B. If the bit is set, automatic recovering from bus
off is disabled and the module remains in bus off state until the bit is cleared by the user. If the bit is cleared before
128 sequences of 11 recessive bits are detected on the CAN bus, then bus off recovery happens as if the
BOFFREC bit had never been set. If the bit is cleared after 128 sequences of 11 recessive bits occurred, FlexCAN
re-synchronizes to the bus by waiting for 11 recessive bits before joining the bus. After clearing, the BOFFREC bit
can be set again during bus off, but it is only effective the next time the module enters bus off. If BOFFREC was
cleared when the module entered bus off, setting it during bus off is not effective for the current bus off recovery.
0 Automatic recovering from bus off state enabled, according to CAN Spec 2.0B
1 Automatic recovering from bus off state disabled
5 Timer synchronize mode. Enables the mechanism that resets the free-running timer each time a message is
TSYN received in Message Buffer 0. This feature provides the means to synchronize multiple FlexCAN stations with a
special SYNC message (global network time).
0 Timer synchronization disabled.
1 Timer synchronization enabled.
Note: There can be a bit clock skew of four to five counts between different FlexCAN modules that are using this
feature on the same network.
4 Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission.
LBUF 0 Message buffer with lowest ID is transmitted first
1 Lowest numbered buffer is transmitted first
23-10
Table 23-3. CANCTRL Field Descriptions (continued)
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MCF52277 Reference Manual, Rev. 1
Description
Freescale Semiconductor