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Overview
1.3.25
DMA Controller
•
16 fully programmable channels with 32-byte transfer control
•
Data movement via dual-address transfers for 8-, 16-, 32- and 128-bit data values
•
Programmable source, destination addresses, transfer size, support for enhanced address modes
•
Support for major and minor nested counters with one request and one interrupt per channel
•
Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed
priority and round-robin channel arbitration
•
External request pins for one channel
1.3.26
General Purpose I/O interface
•
Up to 47 bits of GPIO for the MCF52274 (176 LQFP)
•
Up to 55 bits of GPIO for the MCF52277 (196 MAPBGA)
•
Bit manipulation supported via set/clear functions
•
Various unused peripheral pins may be used as GPIO
1.3.27
System Debug Support
•
Background debug mode (BDM) Revision B+
•
Real time debug support, with four PC breakpoint registers and a pair of address breakpoint
registers with optional data
1.3.28
JTAG Support
•
JTAG part identification and part revision numbers
1.4
Memory Map Overview
Table 1-2
illustrates the overall memory map of the device.
Internal
Address[31:28]
00xx
01xx
1000
1001, 101x
110x
1110
1111
1
The actual size of the SRAM is 128 KByte. However, it may be placed anywhere within the 256 MB space
using the RAMBAR register.
1-10
Table 1-2. System Memory Map
Address Range
0x0000_0000–0x3FFF_FFFF
0x4000_0000–0x7FFF_FFFF
0x8000_0000–0x8FFF_FFFF
0x9000_0000–0xBFFF_FFFF
0xC000_0000–0xDFFF_FFFF
0xE000_0000–0xEFFF_FFFF
0xF000_0000–0xFFFF_FFFF
MCF52277 Reference Manual, Rev. 1
Destination Slave
FlexBus
SDRAM Controller
Internal SRAM
Reserved
FlexBus
Reserved
Internal Peripheral Space
Slave Memory Size
1024 MB
1024 MB
1
256 MB
256 MB
512 MB
256 MB
256 MB
Freescale Semiconductor
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