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Bit 1
Bit 0
RCD1
RCD0
0
0
1
1
0
1
4.2.10
Refresh Control Register (REFCR)
Bit
15
CMF
Initial value
0
Read/Write
R/W*
Bit
7
RFSHE
Initial value
0
Read/Write
R/W
Note: * Only 0 can be written, to clear the flag.
REFCR is a 16-bit readable/writable register that specifies DRAM interface refresh control.
REFCR is initialized to H'0000 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 15—Compare match Flag (CMF): Status flag that indicates a match between the values of
the refresh counter (RTCNT) and the refresh time constant register (RTCOR).
Description
Wait cycle not inserted between RAS assert cycle and CAS assert
cycle
1-state wait cycle inserted between RAS assert cycle and CAS assert
cycle
2-state wait cycle inserted between RAS assert cycle and CAS assert
cycle
3-state wait cycle inserted between RAS assert cycle and CAS assert
cycle
14
13
CMIE
RCW1
0
0
R/W
R/W
6
5
CBRM
RLW1
0
0
R/W
R/W
12
11
RCW0
—
0
0
R/W
R/W
4
3
RLW0
SLFRF
0
0
R/W
R/W
(Initial value)
10
9
RTCK2
RTCK1
0
0
R/W
R/W
2
1
TPCS2
TPCS1
0
0
R/W
R/W
8
RTCK0
0
R/W
0
TPCS0
0
R/W
113
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