Wwdg Registers; Control Register (Wwdg_Cr) - ST STM32F100 Series Reference Manual

RM0041
19.6

WWDG registers

Refer to
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
19.6.1

Control register (WWDG_CR)

Address offset: 0x00
Reset value: 0x0000 007F
31 30 29 28
15 14 13 12
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
Section 2.2 on page 45
27 26 25
11 10 9
Reserved
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter. It is decremented every (4096 x
WDGTB[1:0]
2 ) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6
becomes cleared).
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
WDGA
rs
RM0041 Rev 6
Window watchdog (WWDG)
21 20 19 18
5 4 3 2
T[6:0]
rw
17 16
1 0
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