ARM Cortex-M3 Technical Reference Manual page 10

List of Tables
Table 11-33
Table 12-1
Table 12-2
Table 12-3
Table 12-4
Table 12-5
Table 12-6
Table 12-7
Table 12-8
Table 12-9
Table 12-10
Table 12-11
Table 12-12
Table 12-13
Table 12-14
Table 12-15
Table 12-16
Table 12-17
Table 12-18
Table 12-19
Table 12-20
Table 12-21
Table 12-22
Table 12-23
Table 12-24
Table 12-25
Table 13-1
Table 13-2
Table 13-3
Table 13-4
Table 13-5
Table 13-6
Table 13-7
Table 13-8
Table 13-9
Table 14-1
Table 14-2
Table 14-3
Table 15-1
Table 15-2
Table 15-3
Table 16-1
Table 17-1
Table A-1
Table A-2
Table A-3
x
Bit functions of the AHB-AP ID Register ............................................................... 11-42
JTAG-DP signal connections .................................................................................. 12-3
Standard IR instructions ......................................................................................... 12-8
Recommended implementation-defined IR instructions for IEEE 1149.1-compliance ....
12-9
DPACC and APACC ACK responses ................................................................... 12-12
JTAG target response summary ........................................................................... 12-17
Summary of JTAG host responses ....................................................................... 12-18
Target response summary for DP read transaction requests ............................... 12-33
Target response summary for AP read transaction requests ............................... 12-34
Target response summary for DP write transaction requests ............................... 12-35
Target response summary for AP write transaction requests ............................... 12-36
Summary of host (debugger) responses to the SW-DP acknowledge ................. 12-37
Terms used in SW-DP timing ............................................................................... 12-38
JTAG-DP register map ......................................................................................... 12-47
SW-DP register map ............................................................................................. 12-49
Abort Register bit assignments ............................................................................. 12-50
Identification Code Register bit assignments ........................................................ 12-52
JEDEC JEP-106 manufacturer ID code, with ARM Limited values ...................... 12-53
Control/Status Register bit assignments ............................................................... 12-54
Control of pushed operation comparisons by MASKLANE ................................... 12-56
Transfer Mode, TRNMODE, bit definitions ........................................................... 12-57
Bit assignments for the AP Select Register, SELECT .......................................... 12-58
CTRLSEL field bit definitions ................................................................................ 12-59
Bit assignments for the Wire Control Register (SW-DP only) ............................... 12-61
Turnaround tri-state period field, TURNROUND, bit definitions ........................... 12-61
Wire operating mode, WIREMODE, bit definitions ............................................... 12-62
Trace Out Port signals ............................................................................................ 13-5
ATB Port signals ..................................................................................................... 13-6
Miscellaneous configuration inputs ......................................................................... 13-7
TPIU registers ......................................................................................................... 13-8
Current Output Speed Divisors Register bit assignments ...................................... 13-9
Selected Pin Protocol Register bit assignments ................................................... 13-10
Formatter and Flush Status Register bit assignments .......................................... 13-11
Integration Test Register bit assignments ............................................................ 13-13
Integration Test Register bit assignments ............................................................ 13-13
Instruction fetches ................................................................................................... 14-3
Bus mapper unaligned accesses ............................................................................ 14-9
Memory attributes ................................................................................................. 14-13
Cortex-M3 resources .............................................................................................. 15-4
Exception tracing mapping ................................................................................... 15-11
ETM registers ....................................................................................................... 15-14
ETM interface ports ................................................................................................ 16-3
Instruction timings ................................................................................................... 17-3
Clock signals ............................................................................................................. A-2
Reset signals ............................................................................................................ A-3
Miscellaneous signals ............................................................................................... A-4
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