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Field
Name
[8:5]
POSTCNT
[4:1]
POSTPRESET
[0]
CYCCNTENA
ARM DDI 0337B
Table 11-7 DWT Control Register bit assignments (continued)
Definition
Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1
to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for
PCSAMPLENA or CYCEVTENA use. It also reloads with the value from
POSTPRESET (bits [4:1]).
Reload value for POSTCNT (bits [8:5]) post-scalar counter. If this value is 0, events are
triggered on each tap change (a power of 2, such as 1<<6 or 1<<10). If this field has a
non-0 value, this forms a count-down value (to be reloaded into POSTCNT each time it
reaches 0). For example, a value 1 in this register means an event is formed every other
tap change.
Enable the DWT_CYCCNT counter. If not enabled, the counter does not count and so no
event is generated for PS sampling or CYCCNTENA. The CYCCNT counter should be
initialized to 0 by the debugger in normal use.
Note
The TRCENA bit of the Debug Exception and Monitor Control register must be set
before the DWT can be used. See Debug Exception and Monitor Control Register on
page 10-8.
Note
The DWT is enabled independently from the ITM. If the DWT is enabled to emit events
then the ITM must also be enabled.
DWT Current PC Sampler Cycle Count Register
Use the DWT Current PC Sampler Cycle Count Register to count the number of core
cycles. This count can be used to measure elapsed execution time.
The register address, access type, and Reset state are:
Address
0xE0001004
Access
Read-only
Reset state
0x00000000
Copyright © 2005, 2006 ARM Limited. All rights reserved.
System Debug
11-17
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