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Introduction
1.2.3
NVIC
1.2.4
Bus Matrix
1-8
Memory interface
The processor has a Harvard interface to enable simultaneous instruction fetches with
data/load stores. Memory accesses are controlled by:
•
A separate Load Store Unit (LSU) that decouples load and store operations from
the ALU.
•
A three-word entry prefetch unit. One word is fetched at a time. This can be two
Thumb instructions, one word-aligned Thumb-2 instruction or the upper/lower
halfword of a halfword aligned Thumb-2 instruction. All fetch addresses from the
core are word aligned. If a Thumb-2 instruction is halfword aligned, two fetches
are necessary to fetch the Thumb-2 instruction. However, the 3-entry prefetch
buffer ensures that a stall cycle is only necessary for the first halfword Thumb-2
instruction fetched.
The NVIC is tightly coupled to the processor core. This facilitates low latency exception
processing. The main features include:
•
a configurable number of external interrupts, from 1 to 240
•
a configurable number of bits of priority, from three to eight bits
•
level and pulse interrupt support
•
dynamic reprioritization of interrupts
•
priority grouping
•
support for tail-chaining of interrupts
•
processor state automatically saved on interrupt entry, and restored on interrupt
exit, with no instruction overhead.
Chapter 8 Nested Vectored Interrupt Controller describes the NVIC in detail.
The bus matrix connects the processor and debug interface to the external buses. The
bus matrix interfaces to the following external buses:
•
ICode bus. This is for instruction and vector fetches from code space. This is a
32-bit AHBLite bus.
•
DCode bus. This is for data load/stores and debug accesses to code space. This is
a 32-bit AHBLite bus.
•
System bus. This is for instruction and vector fetches, data load/stores and debug
accesses to system space. This is a 32-bit AHBLite bus.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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