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Instruction type
Size
Extended32
32
Combined Branch
16
Extended
16
Divide
32
Sleep
32
Barriers
16
Saturation
32
ARM DDI 0337B
Cycles count
1
1
1+P
4
0-1
5
2-8
6
1+W
7
1+B
1
Cycle count information:
•
P = pipeline reload
•
N = count of elements
•
W = sleep wait
•
W = sleep wait
In general, each instruction takes one cycle (one core clock) to start executing (as shown
above). Additional cycles may be taken due to fetch stalls.
1.
Branches take one cycle for instruction and then pipeline reload for target
instruction. Non-taken branches are 1 cycle total. Taken branches with an
immediate are normally 1 cycle of pipeline reload (2 cycles total). Taken branches
with register operand are normally 2 cycles of pipeline reload (3 cycles total).
Pipeline reload is longer when branching to unaligned 32-bit instructions as well
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 17-1 Instruction timings (continued)
Description
NOP, Coprocessor (LDC, MCR, MCR2, MCRRMRC,
MRC2, MRRC, and STC), and YIELD (hinted NOP).
Note, no MRS (1), MSR (1), or SUBS (PC return link).
CBZ.
IT and NOP (includes YIELD).
SDIV and UDIV. 32/32 divides both signed and unsigned
with 32-bit quotient result (no remainder, it can be derived
by subtraction). This will early out when dividend and
divisor are close in size.
WFI, WFE, and SEV are in the class of "hinted NOP"
instructions used to control sleep behavior.
ISB, DSB, and DMB are barrier instructions which ensure
certain actions have taken place before the next instruction
is executed.
SSAT and USAT perform saturation on a register. They
perform 3 tasks: normalize the value using shift, test for
overflow from a selected bit position (the Q value) and set
the xPSR Q bit if so, saturate the value if overflow
detected. Saturation refers to the largest unsigned value or
the largest/smallest signed value for the size selected.
Instruction Timing
17-5
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