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Introduction
1.2.2
Processor core
1-6
TPIU
The implementation options for the TPIU are:
•
If the ETM is present in your system, then the TPIU formatter is included.
Otherwise the formatter is not included.
•
A multi-core implementation can be traced by either single or multiple TPIUs.
•
The ARM TPIU block might have been replaced by a partner-specific CoreSight
compliant TPIU.
•
In a production device, the TPIU might have been removed.
Note
There is no Cortex-M3 trace capability if the TPIU has been removed.
SW/JTAG-DP
The implementation options for the SW/JTAG-DP are:
•
Your implementation might contain either or both SW-DP and JTAG-DP.
•
The ARM SW-DP might have been replaced by a partner specific CoreSight
compliant SW-DP.
•
The ARM JTAG-DP might have been replaced by a partner specific CoreSight
compliant JTAG-DP.
•
A partner specific test interface might have been included in parallel with SW-DP
or JTAG-DP.
ROM table
The ROM table is modified from that described in ROM memory table on page 4-8 if:
•
Additional debug components have been added into the system.
The processor core implements the ARMv7-M architecture. It has the following main
features:
•
Thumb-2 Instruction Set Architecture (ISA) subset consisting of all base
Thumb-2 instructions, 16-bit and 32-bit.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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