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Debug Port
12-24
Trn
Turnaround. This is a period during which the line is not driven and the
state of the line is Undefined. The length of the turnaround period is
controlled by the TURNROUND field in the Wire Control Register, see
The Wire Control Register, WCR (SW-DP only) on page 12-60. The
default setting is a turnaround period of one clock cycle.
Note
All the examples given in this chapter show the default turnaround period
of one cycle.
There are additional turnaround periods in the asynchronous SWD
protocol.
Ack
A three-bit target-to-host response. These bits appear on the wire
LSB-first.
WDATA[0:31]
32 bits of write data, from host to target.
Note
The WDATA[0:31] value is transmitted LSB-first on the wire.
RDATA[0:31]
32 bits of read data, from target to host.
Note
The RDATA[0:31] value is transmitted LSB-first on the wire.
Successful write operation (OK response)
A successful write operation consists of three phases:
•
an eight-bit write packet request, from the host to the target
•
a three-bit OK acknowledge response, from the target to the host
•
a 33-bit data write phase, from the host to the target.
By default, there are single-cycle turnaround periods between each of these phases. See
the description of Trn in Key to illustrations of operations on page 12-22 for more
information.
A successful write operation is shown in Figure 12-8 on page 12-25.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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