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Debug Support
5.1
About debug
5-2
The ARM9TDMI debug interface is based on IEEE Std. 1149.1- 1990, Standard Test
Access Port and Boundary-Scan Architecture. Please refer to this standard for an
explanation of the terms used in this chapter and for a description of the TAP controller
states.
The ARM9TDMI contains hardware extensions for advanced debugging features.
These are intended to ease the user's development of application software, operating
systems, and the hardware itself.
The debug extensions allow the core to be stopped by one of the following:
•
a given instruction fetch (breakpoint)
•
a data access (watchpoint)
•
asynchronously by a debug request.
When this happens, the ARM9TDMI is said to be in debug state. At this point, the
internal state of the core and the external state of the system may be examined. Once
examination is complete, the core and system state may be restored and program
execution resumed.
The ARM9TDMI is forced into debug state either by a request on one of the external
debug interface signals, or by an internal functional unit known as the EmbeddedICE
macrocell. Once in debug state, the core isolates itself from the memory system.
The core can then be examined while all other system activity continues as normal.
The internal state of the ARM9TDMI is examined via a JTAG-style serial interface,
which allows instructions to be serially inserted into the pipeline of the core without
using the external data bus. Thus, when in debug state, a store-multiple (STM) could be
inserted into the instruction pipeline, and this would export the contents of the
ARM9TDMI registers. This data can be serially shifted out without affecting the rest of
the system.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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