Table of Contents
Advertisement
Thumb state
TPA
TPIU
Trace Port Interface Unit (TPIU)
Unaligned
UNP
Unpredictable
Warm reset
Watchpoint
Word
Word-invariant
ARM DDI 0337B
A processor that is executing Thumb (16-bit) halfword aligned instructions is operating
in Thumb state.
See Trace Port Analyzer.
See Trace Port Interface Unit.
Drains trace data and acts as a bridge between the on-chip trace data and the data stream
captured by a TPA.
A data item stored at an address that is not divisible by the number of bytes that defines
the data size is said to be unaligned. For example, a word stored at an address that is not
divisible by four.
See Unpredictable.
For reads, the data returned when reading from this location is unpredictable. It can have
any value. For writes, writing to this location causes unpredictable behavior, or an
unpredictable change in device configuration. Unpredictable instructions must not halt
or hang the processor, or any part of the system.
Also known as a core reset. Initializes the majority of the processor excluding the debug
controller and debug logic. This type of reset is useful if you are using the debugging
features of a processor.
A watchpoint is a mechanism provided by debuggers to halt program execution when
the data contained by a particular memory address is changed. Watchpoints are inserted
by the programmer to enable inspection of register contents, memory locations, and
variable values when memory is written to test that the program is operating correctly.
Watchpoints are removed after the program is successfully tested. See also Breakpoint.
A 32-bit data item.
In a word-invariant system, the address of each byte of memory changes when
switching between little-endian and big-endian operation, in such a way that the byte
with address A in one endianness has address A EOR 3 in the other endianness. As a
result, each aligned word of memory always consists of the same four bytes of memory
in the same order, regardless of endianness. The change of endianness occurs because
of the change to the byte addresses, not because the bytes are rearranged.
The ARM architecture supports word-invariant systems in ARMv3 and later versions.
When word-invariant support is selected, the behavior of load or store instructions that
are given unaligned addresses is instruction-specific, and is in general not the expected
behavior for an unaligned access. It is recommended that word-invariant systems use
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Glossary
Glossary-11
Advertisement
Table of Contents
