ARM Cortex-M3 Technical Reference Manual page 27

ARM DDI 0337B
• Memory Protection Unit (MPU). An optional MPU for memory protection.
— Eight memory regions.
— Sub Region Disable (SRD), enabling efficient use of memory regions.
— Background region can be enabled which implements the default memory
map attributes.
• Bus interfaces:
— AHBLite ICode, DCode and System bus interfaces.
— APB Private Peripheral Bus (PPB) Interface
— Bit band support. Atomic bit-band write and read operations.
— Memory access alignment.
— Write buffer. For buffering of write data.
• Low-cost debug solution that features:
— Debug access to all memory and registers in the system, including
Cortex-M3 register bank when the core is running, halted, or held in reset.
— Serial Wire (SW-DP) or JTAG (JTAG-DP) debug access, or both.
— Flash Patch and Breakpoint unit (FPB) for implementing breakpoints and
code patches.
— Data Watchpoint and Trigger unit (DWT) for implementing watchpoints,
trigger resources, and system profiling.
— Instrumentation Trace Macrocell (ITM) for support of printf style
debugging.
— Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer.
— Optional Embedded Trace Macrocell (ETM) for instruction trace.
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Introduction
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