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Debug Port
12-6
Basic operation of the JTAG-DP
The TDI signal into the DAP is the start of the scan chain, and the TDO signal out of
the DAP is the end of the scan chain.
Referring to the DAP State Machine (JTAG) shown in Figure 12-2 on page 12-5:
•
When the JTAG goes through the Capture-IR state, a value is transferred onto the
Instruction Register (IR) scan chain. The IR scan chain is connected between TDI
and TDO.
•
While the JTAG is in the Shift-IR state, and for the transition from Capture-IR to
Shift-IR, the IR scan chain advances one bit for each tick of TCK. This means
that on the first tick, the LSB of the IR is output on TDO, bit [1] of the IR is
transferred to bit [0], bit [2] is transferred to bit [1], and so on. The MSB of the
IR is replaced with the value on TDI.
•
When the JTAG goes through the Update-IR state, the value scanned into the scan
chain is transferred into the Instruction Register.
•
When the JTAG goes through the Capture-DR state, a value is transferred from
one of a number of Data Registers (DRs) onto one of a number of Data Register
scan chains, connected between TDI and TDO.
This data is then shifted while the JTAG is in the Shift-DR state, in the same
manner as the IR shift in the Shift-IR state.
•
When the JTAG goes through the Update-DR state, the value scanned into the
scan chain is transferred into the Data Register
•
When the JTAG is in the Run-Test/Idle state, no special actions occur. Debuggers
can use this as a true resting state.
Note
This is a change from the behavior of previous versions of the ARM Debug
Interface based on the IEEE JTAG standard. From ARM Debug Interface v5,
debuggers do not have to gate the DAP clock to obtain a true rest state.
The behavior of the IR and DR scan chains is described in more detail in IR scan chain
and IR instructions on page 12-7 and DR scan chain and DR registers on page 12-10.
The nTRST signal only resets the JTAG state machine logic. nTRST asynchronously
takes the JTAG state machine logic to the Debug-Logic-Reset state. As shown in
Figure 12-2 on page 12-5, the Debug-Logic-Reset state can also always be entered
synchronously from any state by a sequence of five TCK cycles with TMS high.
However, depending on the initial state of the JTAG, this might take the state machine
through one of the Update states, with the resulting side effects.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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