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Nested Vectored Interrupt Controller
8-18
Field
[19:16]
[15:4]
[3:0]
Interrupt Control State Register
Use the Interrupt Control State Register to:
•
set a pending NMI
•
set or clear a pending SVC
•
set or clear a pending SysTick
•
check for pending exceptions
•
check the vector number of the highest priority pended exception
•
check the vector number of the active exception.
The register address, access type, and Reset state are:
Address
0xE000ED04
Access
Read/write or read-only
Reset state
0x00000000
Figure 8-8 on page 8-19 shows the fields of the Interrupt Control State Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 8-13 CPUID Base Register bit assignments
Name
Definition
Constant
Reads as
PARTNO
Number of processor within family:
[11:10] b11=Cortex family
[9:8] b00=version
[7:6] b00=reserved
[5:4] b10=M (v7-M)
[3:0] X=family member. Cortex-M3 is b0011.
REVISION
Implementation defined revision number.
0xF
ARM DDI 0337B
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