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Core Debug
Bits
R/W
Name
[17]
R/W
MON_PEND
[16]
R/W
MON_EN
[15:11]
-
-
[10]
R/W
VC_HARDERR
[9]
R/W
VC_INTERR
[8]
R/W
VC_BUSERR
[7]
R/W
VC_STATERR
[6]
R/W
VC_CHKERR
[5]
R/W
VC_NOCPERR
[4]
R/W
VC_MMERR
[3:1]
-
-
[0]
R/W
VC_CORERESET
10-10
Table 10-4 Debug Exception and Monitor Control Register (continued)
Function
a
Pend the monitor to activate when priority permits. This can be used to wake
up the monitor through the AHB-AP port. This is the equivalent to C_HALT
for Monitor debug.
This register does not reset on a system reset. It is only reset by a power-on
reset. The debug monitor must be enabled by software in the reset handler or
later, or by the DAP.
Enable the debug monitor. When enabled, the System handler priority register
a
controls its priority level. If disabled, then all debug events go to Hard fault.
C_DEBUGEN in the Debug Halting Control and Statue register overrides this
bit.
Vector catching is semi-synchronous. When a matching event is seen, a Halt
is requested. Because the processor can only halt on an instruction boundary,
it must wait until the next instruction boundary. As a result, it stops on the first
instruction of the exception handler. However, two special cases exist when a
vector catch has triggered:
•
If a fault is taken during vectoring, vector read or stack push error, the
halt occurs on the corresponding fault handler, for the vector error or
stack push.
•
If a late arriving interrupt comes in during vectoring, it is not taken.
That is, an implementation that supports the late arrival optimization
must suppress it in this case.
Reserved, SBZP
b
Debug trap on Hard Fault (see section 8.3).
b
Debug Trap on interrupt/exception service errors (see section 8.3). These are
a subset of other faults and catches before BUSERR or HARDERR.
b
Debug Trap on normal Bus error (see section 8.3).
b
Debug trap on Usage Fault state errors (see section 8.3).
b
Debug trap on Usage Fault enabled checking errors (see section 8.3).
b
Debug trap on Usage Fault access to Coprocessor which is not present or
marked as not present in CAR register.
b
Debug trap on Memory Management faults (see section 8.3).
Reserved, SBZP
b
Reset Vector Catch. Halt running system if Core reset occurs.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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