Table of Contents
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Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
ARM DDI 0337B
10.2
Core debug registers ................................................................................ 10-3
10.3
Core debug access example .................................................................. 10-12
10.4
Using application registers in core debug ............................................... 10-13
System Debug
11.1
About system debug ................................................................................. 11-2
11.2
System Debug Access .............................................................................. 11-3
11.3
System debug programmer's model ......................................................... 11-5
11.4
Flash Patch and Breakpoint ...................................................................... 11-6
11.5
Data Watchpoint and Trace .................................................................... 11-13
11.6
Instrumentation Trace Macrocell ............................................................. 11-28
11.7
AHB Access Port .................................................................................... 11-37
Debug Port
12.1
About the Debug Port ............................................................................... 12-2
12.2
JTAG-DP ................................................................................................... 12-3
12.3
SW-DP .................................................................................................... 12-20
12.4
Common Debug Port (DP) features ........................................................ 12-41
12.5
Debug Port Programmer's Model ............................................................ 12-47
Trace Port Interface Unit
13.1
About the Trace Port Interface Unit .......................................................... 13-2
13.2
TPIU registers ........................................................................................... 13-8
Bus Interface
14.1
About bus interfaces ................................................................................. 14-2
14.2
ICode bus interface ................................................................................... 14-3
14.3
DCode bus interface ................................................................................. 14-5
14.4
System interface ....................................................................................... 14-6
14.5
External private peripheral interface ......................................................... 14-8
14.6
Access alignment ...................................................................................... 14-9
14.7
Unaligned accesses that cross regions ................................................... 14-10
14.8
Bit-band accesses ................................................................................... 14-11
14.9
Write buffer ............................................................................................. 14-12
14.10
Memory attributes ................................................................................... 14-13
Embedded Trace Macrocell
15.1
About the ETM .......................................................................................... 15-2
15.2
Data tracing ............................................................................................... 15-6
15.3
ETM Resources ........................................................................................ 15-7
15.4
Trace output .............................................................................................. 15-9
15.5
ETM architecture ..................................................................................... 15-10
15.6
ETM programmer's model ....................................................................... 15-14
Embedded Trace Macrocell Interface
16.1
About the ETM interface ........................................................................... 16-2
Copyright © 2005, 2006 ARM Limited. All rights reserved.
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