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Name of register
ISAR4: ISA Feature register4
Software Trigger Interrupt Register
Peripheral identification register (PERIPHID4)
Peripheral identification register (PERIPHID5)
Peripheral identification register (PERIPHID6)
Peripheral identification register (PERIPHID7)
Peripheral identification register Bits 7:0 (PERIPHID0)
Peripheral identification register Bits 15:8 (PERIPHID1)
Peripheral identification register Bits 23:16 (PERIPHID2)
Peripheral identification register Bits 31:24 (PERIPHID3)
Component identification register Bits 7:0 (PCELLID0)
Component identification register Bits 15:8 (PCELLID1)
Component identification register Bits 23:16 (PCELLID2)
Component identification register Bits 31:24 (PCELLID3)
a. Reset value depends on the number of interrupts defined.
3.1.2
Core debug registers
Name of register
Debug Halting Control and Status Register
Debug Core Register Selector Register
Debug Core Register Data Register
Debug Exception and Monitor Control Register.
ARM DDI 0337B
Table 3-2 gives a summary of the core debug registers. For a detailed description of the
core debug registers, see Chapter 10 Core Debug.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 3-1 NVIC registers (continued)
Type
Address
Read-only
0xE000ED70
0xE000EF00
Write Only
0xE000EFD0
Read-only
0xE000EFD4
Read-only
0xE000EFD8
Read-only
0xE000EFDC
Read-only
0xE000EFE0
Read-only
0xE000EFE4
Read-only
0xE000EFE8
Read-only
0xE000EFEC
Read-only
0xE000EFF0
Read Only
Read-only
0xE000EFF4
Read-only
0xE000EFF8
0xE000EFFC
Read-only
Table 3-2 Core debug registers
Type
Address
Read/Write
0xE000EDF0
Write-only
0xE000EDF4
Read/Write
0xE000EDF8
Read/Write
0xE000EDFC
System Control
Reset value
0x01310102
-
0x04
0x00
0x00
0x00
0x00
0xB0
0x0B
0x00
0x0D
0xE0
0x05
0xB1
Reset Value
a
0x00000000
-
-
b
0x00000000
3-5
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