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Exceptions
5.3.1
Priority levels
5.3.2
Priority grouping
5-6
The NVIC supports software-assigned priority levels. You can assign a priority level
from 0 to 255 to an interrupt by writing to the eight-bit PRI_N field in an Interrupt
Priority Register, see Interrupt Priority Registers on page 8-15. Hardware priority
decreases with increasing interrupt number. Priority level 0 is the highest priority level,
and priority level 255 is the lowest. The priority level overrides the hardware priority.
For example, if you assign priority level 1 to INTISR[0] and priority level 0 to
INTISR[31], then INTISR[31] has higher priority than INTISR[0].
Note
Software prioritization does not affect Reset, NMI, and Hard Fault. They always have
higher priority than the external interrupts.
If you assign the same priority level to two or more interrupts, their hardware priorities
determine the order in which the processor activates them. For example, if both
INTISR[0] and INTISR[1] are priority level 1, then INTISR[0] has higher priority
than INTISR[1].
For more information on the PRI_N fields, see Interrupt Priority Registers on
page 8-15.
To increase priority control in systems with large numbers of interrupts, the NVIC
supports priority grouping. You can use the PRIGROUP field in the Application
Interrupt and Reset Control Register on page 8-21 to split the value in every PRI_N
field into a pre-emption priority field and a subpriority field. The pre-emption priority
group is referred to as the group priority. Where multiple pending exceptions share the
same group priority, the sub-priority bit field is then used to resolve the priority within
a group. This is referred to as the sub-priority within the group. The combination of the
group priority and the sub-priority is referred to generally as the priority. Where two
pending exceptions have the same priority, the lower pending exception number has
priority over the higher pending exception number. This is consistent with the priority
precedence scheme.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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