Table of Contents
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Operation
Bitwise AND register value with complement of immediate
12-bit value
Bitwise AND register value with complement of shifted
register value
Branch with link
Branch with link (immediate)
Unconditional branch
Return number of leading zeros in register value
Compare register value with two's complement of immediate
12-bit value
Compare register value with two's complement of shifted
register value
Compare register value with immediate 12-bit value
Compare register value with shifted register value
Data memory barrier
Data synchronization barrier
Exclusive OR register value with immediate 12-bit value
Exclusive OR register value with shifted register value
Instruction synchronization barrier
Load multiple memory registers, increment after or decrement
before
Memory word from base register address + immediate 12-bit
offset
Memory word to PC from register address + immediate 12-bit
offset
Memory word to PC from base register address immediate
8-bit offset, postindexed
Memory word from base register address immediate 8-bit
offset, postindexed
ARM DDI 0337B
Table 1-2 32-bit Cortex-M3 instruction summary (continued)
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Assembler
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
BL <label>
BL<c> <label>
B.W <label>
CLZ.W <Rd>, <Rn>
CMN.W <Rn>, #<modify_constant(immed_12)>
CMN.W <Rn>, <Rm>{, <shift>}
CMP.W <Rn>, #<modify_constant(immed_12)>
CMP.W <Rn>, <Rm>{, <shift>}
DMB <c>
DSB <c>
EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
ISB <c>
LDM{IA|DB}.W <Rn>{!}, <registers>
LDR.W <Rxf>, [<Rn>, #<offset_12>]
LDR.W PC, [<Rn>, #<offset_12>]
LDR.W PC, #<+/-<offset_8>
LDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Introduction
1-17
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