ARM Cortex-M3 Technical Reference Manual page 15

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ARM DDI 0337B
AHB-AP ID Register .............................................................................................. 11-42
JTAG-DP physical connection ................................................................................ 12-4
The DAP State Machine (JTAG) ............................................................................. 12-5
JTAG Instruction Register bit order ......................................................................... 12-7
JTAG Bypass Register operation .......................................................................... 12-10
JTAG Device ID Code Register bit order .............................................................. 12-11
Bit order of JTAG DP and AP Access Registers ................................................... 12-13
JTAG-DP ABORT scan chain bit order ................................................................. 12-19
Serial Wire Debug successful write operation ....................................................... 12-25
Serial Wire Debug successful read operation ....................................................... 12-25
Serial Wire Debug WAIT response to a packet request ........................................ 12-26
Serial Wire Debug FAULT response to a packet request ..................................... 12-26
Serial Wire Debug protocol error after a packet request ....................................... 12-27
Serial Wire WAIT or FAULT response to a read operation when overrun detection is en-
abled ..................................................................................................................... 12-31
Serial Wire WAIT or FAULT response to a write operation when overrun detection is en-
abled ..................................................................................................................... 12-31
SW-DP acknowledgement timing .......................................................................... 12-38
SW-DP to DAP bus timing for writes ..................................................................... 12-39
SW-DP to DAP bus timing for reads ..................................................................... 12-39
SW-DP idle timing ................................................................................................. 12-40
Pushed operations overview ................................................................................. 12-44
Abort Register bit assignments ............................................................................. 12-50
Identification Code Register bit assignments ........................................................ 12-52
Control/Status Register bit assignments ............................................................... 12-54
Bit assignments for the AP Select Register, SELECT .......................................... 12-58
Bit assignments for the Wire Control Register (SW-DP only) ............................... 12-60
Block diagram of the TPIU (non-ETM version) ........................................................ 13-3
Block diagram of the TPIU (ETM version) ............................................................... 13-4
Supported Port Size Register bit assignments ........................................................ 13-9
Current Output Speed Divisors Register bit assignments ....................................... 13-9
Selected Pin Protocol Register bit assignments .................................................. 13-10
Formatter and Flush Status Register bit assignments ......................................... 13-11
Integration Test Register bit assignments ............................................................. 13-12
Integration Test Register bit assignments ............................................................. 13-13
ETM block diagram ................................................................................................. 15-3
Exception return packet encoding ......................................................................... 15-10
Exception encoding for branch packet .................................................................. 15-13
Conditional branch backwards not taken ................................................................ 16-5
Conditional branch backwards taken ...................................................................... 16-5
Conditional branch forwards not taken .................................................................... 16-6
Conditional branch forwards taken ......................................................................... 16-6
Unconditional branch without pipeline stalls .......................................................... 16-6
Unconditional branch with pipeline stalls ............................................................... 16-7
Unconditional branch in execute aligned ................................................................ 16-7
Unconditional branch in execute unaligned ............................................................ 16-7
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