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Exceptions
5-22
setup peripherals, etc)
nvic[INT_ENA] = 1;
while (1)
{
// do some work for (exc_req = FALSE; exc_req == FALSE; )
wfi(); // sleep now - wait for interrupt
// do some post exception checking/cleanup
}
}
Example 5-3 Reset routine with selected Sleep on exit cancelled by ISRs that
void reset()
{
// do setup work (initialize variables, initialize runtime if wanted,
setup peripherals, etc)
nvic[INT_ENA] = 1;
while (1)
{
// We are slept until an exception clears sleep on exit state so that we
can post-process/cleanup.
nvic_regs[NV_SLEEP] |= NVSLEEP_ON_EXIT;
while (nvic_regs[NV_SLEEP] & NVSLEEP_ON_EXIT)
wfi(); // sleep now - wait for interrupt which clears
// do some post exception checking/cleanup
}
}
Note
An executive does not need to live in the Reset routine because priority level changes
can be enacted from an ISR activation. This ensures faster response to changing loads,
and uses priority boosting, to solve priority inversions, to ensure fine grain support. For
RTOS models using threads and privilege, the Thread Mode is used for the user code.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
// enable interrupts
// enable interrupts
require attention
ARM DDI 0337B
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