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Debug Support
8.1
About the debug interface
8.1.1
Stages of debug
8-2
The ARM966E-S debug interface is based on IEEE Std. 1149.1- 1990, Standard Test
Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation
of the terms used in this chapter and for a description of the TAP controller states.
The ARM9E-S processor core within the ARM966E-S contains hardware extensions
for advanced debugging features. These make it easier to develop application software,
operating systems, and the hardware itself.
The debug extensions allow you to force the core into debug state. In debug state, the
core and ARM966E-S memory system are effectively stopped, and isolated from the
rest of the system. This is known as halt mode operation and allows the internal state of
the ARM9E-S core, ARM966E-S system, and external state of the AHB to be examined
while all other system activity continues as normal. When debug is complete, the
ARM9E-S restores the core and system state, and resumes program execution.
In addition, the ARM9E-S supports a real-time debug mode, where instead of
generating a breakpoint or watchpoint, an internal Instruction Abort or Data Abort is
generated. This is known as monitor mode operation.
When used in conjunction with a debug monitor program activated by the abort
exception entry, You can debug the ARM966E-S while allowing the execution of
critical interrupt service routines. The debug monitor program typically communicates
with the debug host over the ARM966E-S debug communication channel. Monitor
mode debug is described in Monitor mode debug on page 8-23.
A request on one of the external debug interface signals, or on an internal functional unit
known as the EmbeddedICE-RT logic, forces the ARM9E-S into debug state. The
interrupts that activate debug are:
•
a breakpoint (a given instruction fetch)
•
a watchpoint (a data access)
•
an external debug request.
The internal state of the ARM9E-S is examined using a JTAG-style serial interface,
allowing instructions to be serially inserted into the core pipeline without using the
external data bus. For example, when in debug state, a STore Multiple (
inserted into the instruction pipeline, and this exports the contents of the ARM9E-S
registers. This data can be serially shifted out without affecting the rest of the system.
Copyright © 2000 ARM Limited. All rights reserved.
) can be
STM
ARM DDI 0186A
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