ARM Cortex-M3 Technical Reference Manual page 38

Introduction
Operation
Compare registers
Compare high register to low or high register
Change processor state
Copy high or low register value to another high or low register
Bitwise exclusive OR register values
Condition the following instruction, Condition the following two instructions,
Condition the following three instructions, Condition the following four
instructions
Multiple sequential memory words
Load memory word from base register address + 5-bit immediate offset
Load memory word from base register address + register offset
Load memory word from PC address + 8-bit immediate offset
Load memory word from SP address + 8-bit immediate offset
Load memory byte [7:0] from register address + 5-bit immediate offset
Load memory byte [7:0] from register address + register offset
Load memory halfword [15:0] from register address + 5-bit immediate offset
Load halfword [15:0] from register address + register offset
Load signed byte [7:0] from register address + register offset
Load signed halfword [15:0] from register address + register offset
Logical shift left by immediate number
Logical shift left by number in register
Logical shift right by immediate number
Logical shift right by number in register
Move immediate 8-bit value to register
Move low register value to low register
Move high or low register value to high or low register
1-14
Table 1-1 16-bit Cortex-M3 instruction summary (continued)
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Assembler
CMP <Rn>, <Rm>
CMP <Rn>, <Rm>
CPS <effect>, <iflags>
CPY <Rd> <Rm>
EOR <Rd>, <Rm>
IT <cond> IT<x> <cond> IT<x><y>
<cond> IT<x><y><z> <cond>
LDMIA <Rn>!, <registers>
LDR <Rd>, [<Rn>, #<immed_5> * 4]
LDR <Rd>, [<Rn>, <Rm>]
LDR <Rd>, [PC, #<immed_8> * 4]
LDR, <Rd>, [SP, #<immed_8> * 4]
LDRB <Rd>, [<Rn>, #<immed_5>]
LDRB <Rd>, [<Rn>, <Rm>]
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
LDRH <Rd>, [<Rn>, <Rm>]
LDRSB <Rd>, [<Rn>, <Rm>]
LDRSH <Rd>, [<Rn>, <Rm>]
LSL <Rd>, <Rm>, #<immed_5>
LSL <Rd>, <Rs>
LSR <Rd>, <Rm>, #<immed_5>
LSR <Rd>, <Rs>
MOV <Rd>, #<immed_8>
MOV <Rd>, <Rn>
MOV <Rd>, <Rm>
ARM DDI 0337B