ARM Cortex-M3 Technical Reference Manual page 130

Clocking and Resets
6.3.4 SW-DP reset
6.3.5 Normal operation
6-8
You do not have to synchronize the nTRST signal because it is synchronized within the
processor, as shown in Figure 6-3 on page 6-7.
SW-DP is reset with SWRSTn. This reset must be synchronized to SWCLK.
During normal operation, neither processor reset nor power-on reset is asserted. If the
JTAG-DP port is not being used, the value of nTRST does not matter.
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