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Bits
Access
Function
[11:8]
R/W
MASKLANE
[7]
a
RO
WDATAERR
[6]
a
RO
READOK
[5]
b
STICKYERR
RO
[4]
b
STICKYCMP
RO
[3:2]
R/W
TRNMODE
ARM DDI 0337B
Table 12-18 Control/Status Register bit assignments (continued)
Description
Indicates the bytes to be masked in pushed compare and
pushed verify operations. See MASKLANE and the bit
masking of the pushed compare and pushed verify
operations on page 12-56.
After a reset the value of this field is Unpredictable.
a
This bit is set to 1 if a Write Data Error occurs. It is set if:
•
there is a a parity or framing error on the data phase
of a write
•
a write that has been accepted by the DP is then
discarded without being submitted to the AP.
This bit can only be cleared by writing b1 to the
WDERRCLR field of the Abort Register, see The Abort
Register, ABORT on page 12-49.
After a reset this bit is Low (0).
a
This bit is set to 1 if the response to a previous AP or
RDBUFF was OK. It is cleared to 0 if the response was not
OK.
This flag always indicates the response to the last AP read
access.
After a reset this bit is Low (0).
This bit is set to 1 if an error is returned by an AP
transaction. To clear this bit:
On a JTAG-DP Write b1 to this bit of this register.
On a SW-DP Write b1 to the STKERRCLR field of the
After a reset this bit is Low (0).
This bit is set to 1 when a match occurs on a pushed
compare or a pushed verify operation. To clear this bit:
On a JTAG-DP Write b1 to this bit of this register.
On a SW-DP Write b1 to the STKCMPCLR field of the
After a reset this bit is Low (0).
This field sets the transfer mode for AP operations, see
Transfer mode (TRNMODE), bits [3:2] on page 12-57.
After a reset the value of this field is Unpredictable.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Abort Register, see The Abort Register,
ABORT on page 12-49.
Abort Register, see The Abort Register,
ABORT on page 12-49.
Debug Port
Required?
Yes
a
Yes
a
Yes
Yes
Yes
Yes
12-55
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