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10.2
About the Cortex-A9 debug interface
ARM DDI 0388I
ID073015
The Cortex-A9 processor implements the ARMv7 debug architecture as described in the ARM
Architecture Reference Manual.
In addition, there are:
•
Cortex-A9 processor specific events. These are described in
events on page
11-7.
•
System coherency events.
For more information, see
Monitoring
Unit.
The debug interface consists of:
•
a Baseline CP14 interface
•
an Extended CP14 interface
•
an external debug interface connected to the external debugger through a Debug Access
Port (DAP).
Figure 10-2
shows the Cortex-A9 debug registers interface.
Cross-trigger
interface
System
bus
Baseline
CP14
interface
Cortex-A9
and
processor
Extended
CP14
interface
Figure 10-2 Debug registers interface and CoreSight infrastructure
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Non-Confidential
Performance monitoring on page 2-3
Cross-trigger
Matrix (CTM)
VSoc power domain
Vcore power domain
Debug
registers
Debug APB
Performance monitoring
and
Chapter 11 Performance
Debug
Access
ROM map
Port
Interconnect
(optional)
(DAP)
(optional)
Debug
Debug
10-3
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