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Instruction Timing
17-8
segment, and unaligned). Further, if the STR is followed by ALU operations (not
a load or store), then the processor will drain the store without waiting at all. So,
load-store operations should be avoided after STR instructions when possible.
•
LDREX and STREX may be pipelined exactly as LDR. Because STREX is
treated more like an LDR, it may be pipelined as explained for LDR. Equally
LDREX is treated exactly as an LDR and so may be pipelined.
•
LDRD, STRD may not be pipelined with preceding or following instructions.
However, the two words are pipelined together. So, three cycles when not stalled.
•
LDM, STM, LDC, STC may not be pipelined with preceding or following
instructions. However, all elements after the first are pipelined together. So, a
three element LDM will take 2+1+1 or 5 cycles when not stalled. Likewise, an
eight element store will take nine cycles when not stalled. When interrupted,
LDM and STM instructions will continue from where left off when returned to.
The continue operation will add one or two cycles to the first element to get
started.
•
Unaligned Word or Halfword Loads or stores will add penalty cycles. A byte
aligned halfword load or store will add one extra cycle to perform the operation
as two bytes. A halfword aligned word load or store will add one extra cycle to
perform the operation as two halfwords. A byte-aligned word load or store will
add two extra cycles to perform the operation as a byte, a halfword, and a byte.
These numbers will be increased if the memory stalls. A STR or STRH may not
delay the processor due to the store buffer.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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