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Nested Vectored Interrupt Controller
Field
Name
[3]
UNALIGN_TRP
[1]
USERSETMPEND
[0]
NONEBASETHRDENA
8-26
Definition
Trap for unaligned access. This enables faulting/halting on any unaligned half or
full word access. Unaligned load-store multiples always fault. The relevant Usage
Fault Status Register bit is UNALIGNED, see Usage Fault Status Register on
page 8-33.
If written as 1, enables user code to write the Software Trigger Interrupt register to
trigger (pend) a Main exception, which is one associated with the Main stack
pointer.
When 0, default, Thread mode can only be entered when returning from the last
exception. When set to 1, Thread mode can be entered from any level in Handler
mode by controlled return value.
System Handler Priority Registers
Use the three System Handler Priority Registers to prioritize the following system
handlers:
•
memory manage
•
bus fault
•
usage fault
•
debug monitor
•
SVC
•
SysTick
•
PendSV
System handlers are a special class of exception handler that can have their priority set
to any of the priority levels. Most can be masked on (enabled) or off (disabled). When
disabled, the fault is always treated as a Hard Fault.
The register addresses, access types, and Reset states are:
Address
0xE000ED18
Access
Read/write
Reset state
0x00000000
Figure 8-13 on page 8-27 shows the fields of the System Handler Priority Registers.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 8-18 Configuration Control Register bit assignments
,
,
0xE000ED1C
0xE000ED20
ARM DDI 0337B
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