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Debug Port
12-16
Once the previous transaction has completed, further APACC transactions are
abandoned and scans respond immediately with an OK/FAULT response. However, DP
registers can be accessed. In particular the CTRL/STAT register can be accessed, to
confirm that the Sticky Overrun flag is set, and to clear the flag after gathering any
required information about the overrun condition. See Overrun detection on page 12-42
for more information.
Minimum response times
As explained in The OK/FAULT response to a DPACC or APACC access on page 12-13,
a DP or AP register access is initiated at the Update-DR state of one DPACC or APACC
access, and the result of the access is returned at the Capture-DR state of the following
DPACC or APACC access. However, the second access generates a WAIT response if
the requested register access has not completed.
The JTAG clock, TCK, is asynchronous to the internal clock of the system being
debugged, and the time required for an access to complete includes clock cycles in both
domains. However, the timing between the Update-DR state and the Capture-DR state
only includes TCK cycles. Referring to Figure 12-2 on page 12-5, there are two paths
from the Update-DR state, where the register access is initiated, to the Capture-DR
state, where the response is captured:
•
a direct path through Select-DR-Scan
•
a path through Run-Test/Idle and Select-DR-Scan.
If the second path is followed, the state machine can spend any number of TCK cycles
spinning in the Run-Test/Idle state. This means it is possible to vary the number of TCK
cycles between the Update-DR and Capture-DR states.
A JTAG implementation might impose an implementation-defined lower limit on the
number of TCK cycles between the Update-DR and Capture-DR states, and always
generate an immediate WAIT response if Capture-DR is entered before this limit has
expired. Although any debugger must be able to recover successfully from any WAIT
response, ARM Limited recommends that debuggers should be able to adapt to any
Implementation-defined limit.
In addition, when accessing AP registers, or accessing a connected device through an
AP, there might be other variable response delays in the system. A debugger that can
adapt to these delays, avoiding wasted WAIT scans, operates more efficiently and
provides higher maximum data throughput.
Target response summary
As described in The OK/FAULT response to a DPACC or APACC access on page 12-13
and Minimum response times, a DP or AP register access is initiated at the Update-DR
state of one DPACC or APACC access, and the result of the access is returned at the
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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