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Monitor debug-mode
MPU
Multi-layer
Penalty
Power-on reset
PPB
Prefetching
Prefetch Abort
Private Peripheral Bus
Processor
RealView ICE
Reserved
ARM DDI 0337B
One of two mutually exclusive debug modes. In Monitor debug-mode the processor
enables a software abort handler provided by the debug monitor or operating system
debug task. When a breakpoint or watchpoint is encountered, this enables vital system
interrupts to continue to be serviced while normal program execution is suspended.
See also Halt mode.
See Memory Protection Unit.
An interconnect scheme similar to a cross-bar switch. Each master on the interconnect
has a direct link to each slave, The link is not shared with other masters. This enables
each master to process transfers in parallel with other masters. Contention only occurs
in a multi-layer interconnect at a payload destination, typically the slave.
The number of cycles in which no useful Execute stage pipeline activity can occur
because an instruction flow is different from that assumed or predicted.
See Cold reset.
See Private Peripheral Bus.
In pipelined processors, the process of fetching instructions from memory to fill up the
pipeline before the preceding instructions have finished executing. Prefetching an
instruction does not mean that the instruction has to be executed.
An indication from a memory system to the core that an instruction has been fetched
from an illegal memory location. An exception must be taken if the processor attempts
to execute the instruction. A Prefetch Abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction memory.
See also Data Abort, Abort.
Memory space at
0xE0000000
A processor is the circuitry in a computer system required to process data using the
computer instructions. It is an abbreviation of microprocessor. A clock source, power
supplies, and main memory are also required to create a minimum complete working
computer system.
A system for debugging embedded processor cores using a JTAG interface.
A field in a control register or instruction format is reserved if the field is to be defined
by the implementation, or produces Unpredictable results if the contents of the field are
not zero. These fields are reserved for use in future extensions of the architecture or are
implementation-specific. All reserved bits not used by the implementation must be
written as 0 and read as 0.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
to
.
0xE00FFFFF
Glossary
Glossary-9
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