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14.4.5
Memory attributes
14.4.6
Pipelined instruction fetches
ARM DDI 0337B
The processor exports memory attributes on the System bus by using a sideband bus
called MEMATTRS. For more information, see Memory attributes on page 14-13.
To provide a clean timing interface on the System bus, instruction and vector fetch
requests to this bus are registered. This results in an additional cycle of latency because
instructions fetched from the System bus take two cycles. This also means that
back-to-back instruction fetches from the System bus are not possible.
Note
Instruction fetch requests to the ICode bus are not registered. Performance critical code
should be run from the ICode interface.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Bus Interface
14-7
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