ARM Cortex-M3 Technical Reference Manual page 159

Table 8-16 Application Interrupt and Reset Control Register bit assignments (continued)
Field Name
[7:3] -
[2] SYSRESETREQ
[1] VECTCLRACTIVE
[0] VECTRESET
ARM DDI 0337B
Definition
PRIGROUP field is a binary point position indicator for creating subpriorities for
exceptions that share the same pre-emption level. It divides the PRI_n field in the
Interrupt Priority Register into a pre-emption level and a subpriority level. The binary
point is a left-of value. This means that the PRIGROUP value represents a point
starting at the left of the LSB. This is bit 0 of 7:0.
The lowest value might not be 0 depending on the number of bits allocated for
priorities, and implementation choices.
Reserved.
Causes a signal to be asserted to the outer system that indicates a reset is requested.
Intended to force a large system reset of all major components except for debug.
Setting this bit does not prevent Halting Debug from running.
Clear active vector bit:
1 = clear all state information for active NMI, fault, and interrupts
0 = do not clear.
It is the responsibility of the application to reinitialize the stack.
The VECTCLRACTIVE bit is for returning to a known state during debug. The
VECTCLRACTIVE bit self-clears.
IPSR is not cleared by this operation. So, if used by an application, it must only be
used at the base level of activation, or within a system handler whose active bit can be
set.
System Reset bit. Resets the system, with the exception of debug components:
1 = reset system
0 = do not reset system.
The VECTRESET bit self-clears. Reset clears the VECTRESET bit.
For debugging, only write this bit when the core is halted.
System Control Register
Use the System Control Register for power-management functions:
• signal to the system when the Cortex-M3 processor can enter a low power state
• control how the processor enters and exits low power states.
The register address, access type, and Reset state are:
Address
0xE000ED10
Access Read/write
Reset state 0x00000000
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Nested Vectored Interrupt Controller
8-23