ARM Cortex-M3 Technical Reference Manual page 4

Contents
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
iv
Memory Map
4.1 About the memory map .............................................................................. 4-2
4.2 Bit-banding ................................................................................................. 4-5
4.3 ROM memory table .................................................................................... 4-8
Exceptions
5.1 About the exception model ......................................................................... 5-2
5.2 Exception types .......................................................................................... 5-3
5.3 Exception priority ........................................................................................ 5-5
5.4 Privilege and stacks .................................................................................... 5-8
5.5 Pre-emption .............................................................................................. 5-10
5.6 Tail-chaining ............................................................................................. 5-13
5.7 Late-arriving .............................................................................................. 5-14
5.8 Exit ............................................................................................................ 5-16
5.9 Resets ...................................................................................................... 5-19
5.10 Exception control transfer ......................................................................... 5-23
5.11 Setting up multiple stacks ......................................................................... 5-24
5.12 Abort model .............................................................................................. 5-26
5.13 Activation levels ........................................................................................ 5-31
5.14 Flowcharts ................................................................................................ 5-33
Clocking and Resets
6.1 Cortex-M3 clocking ..................................................................................... 6-2
6.2 Cortex-M3 resets ........................................................................................ 6-4
6.3 Cortex-M3 reset modes .............................................................................. 6-5
Power Management
7.1 About power management ......................................................................... 7-2
7.2 System power management ....................................................................... 7-3
Nested Vectored Interrupt Controller
8.1 About the NVIC ........................................................................................... 8-2
8.2 NVIC programmer's model ......................................................................... 8-3
8.3 Level versus pulse interrupts .................................................................... 8-39
Memory Protection Unit
9.1 About the MPU ........................................................................................... 9-2
9.2 MPU programmer's model .......................................................................... 9-3
9.3 MPU access permissions ......................................................................... 9-14
9.4 MPU aborts ............................................................................................... 9-16
9.5 Updating an MPU region .......................................................................... 9-17
9.6 Interrupts and updating the MPU .............................................................. 9-20
Core Debug
10.1 About core debug ..................................................................................... 10-2
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