ARM Cortex-M3 Technical Reference Manual page 8

List of Tables
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 5-13
Table 5-14
Table 5-15
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 8-14
Table 8-15
Table 8-16
Table 8-17
Table 8-18
Table 8-19
Table 8-20
Table 8-21
Table 8-22
Table 8-23
Table 8-24
Table 8-25
Table 8-26
Table 8-27
Table 8-28
Table 9-1
viii
Priority grouping ........................................................................................................ 5-7
Exception entry steps ............................................................................................. 5-11
Exception exit steps ................................................................................................ 5-16
Exception return behavior ....................................................................................... 5-18
Reset actions .......................................................................................................... 5-19
Reset boot-up behavior .......................................................................................... 5-20
Transferring to exception processing ...................................................................... 5-23
Faults ...................................................................................................................... 5-27
Debug faults ............................................................................................................ 5-29
Fault status and fault address registers .................................................................. 5-30
Privilege and stack of different activation levels ..................................................... 5-31
Exception transitions ............................................................................................... 5-31
Exception subtype transitions ................................................................................. 5-32
Cortex-M3 processor clocks ..................................................................................... 6-2
Cortex-M3 macrocell clocks ...................................................................................... 6-2
Reset inputs .............................................................................................................. 6-4
Reset modes ............................................................................................................. 6-5
Supported sleep modes ........................................................................................... 7-3
NVIC registers .......................................................................................................... 8-3
Interrupt Controller Type Register bit assignments .................................................. 8-7
SysTick Control and Status Register bit assignments ............................................. 8-8
SysTick Reload Value Register bit assignments ...................................................... 8-9
SysTick Current Value Register bit assignments .................................................... 8-10
SysTick Calibration Value Register bit assignments .............................................. 8-11
Bit functions of the Interrupt Set-Enable Register ................................................... 8-12
Bit functions of the Interrupt Clear-Enable Register ............................................... 8-12
Bit functions of the Interrupt Set-Pending Register ................................................. 8-13
Bit functions of the Interrupt Clear-Pending Registers ............................................ 8-14
Bit functions of the Active Bit Register .................................................................... 8-14
Interrupt Priority Registers 0-31 bit assignments .................................................... 8-16
CPUID Base Register bit assignments ................................................................... 8-16
Interrupt Control State Register bit assignments .................................................... 8-18
Vector Table Offset Register bit assignments ........................................................ 8-20
Application Interrupt and Reset Control Register bit assignments ......................... 8-21
System Control Register bit assignments ............................................................... 8-23
Configuration Control Register bit assignments ..................................................... 8-24
System Handler Priority Registers bit assignments ................................................ 8-26
System Handler Control and State Register bit assignment ................................... 8-27
Memory Manage Fault Status Register bit assignments ........................................ 8-30
Bus Fault Status Register bit assignments ............................................................. 8-31
Usage Fault Status Register bit assignments ......................................................... 8-33
Hard Fault Status Register bit assignments ........................................................... 8-34
Debug Fault Status Register bit assignments ......................................................... 8-36
Bit functions of the Memory Manage Fault Address Register ................................. 8-37
Bit functions of the Bus Fault Address Register ..................................................... 8-37
Software Trigger Interrupt Register bit assignments .............................................. 8-38
MPU registers ........................................................................................................... 9-3
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