Table of Contents
Advertisement
System Debug
Field
Name
[17]
CPIEVTENA
[16]
EXCTRCENA
[15:13]
-
[12]
PCSAMPLEENA
[11:10]
SYNCTAP
[9]
CYCTAP
11-16
Table 11-7 DWT Control Register bit assignments (continued)
Definition
Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256
cycles of multi-cycle instructions).
1 = CPI counter events enabled
0 = CPI counter events disabled.
Reset clears the CPIEVTENA bit.
Enables Interrupt event tracing:
1 = interrupt event trace enabled
0 = interrupt event trace disabled.
Reset clears the EXCEVTENA bit.
Reserved
Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter
triggers it. See CYCTAP (bit [9]) and POSTPRESET (bits [4:1]) for details. Enabling this
bit overrides CYCEVTENA (bit [20]).
1 = PC Sampling event enabled
0 = PC Sampling event disabled
Reset clears the PCSAMPLENA bit.
This is used to feed a synchronization pulse to the ITM SYNCEN control. The value
selected here picks the rate (should be about 1/second or less) by selecting a "tap" on the
DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect
synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its
values, and SYNCEN must be set to 1.
0b00 Disabled. No synch counting
0b01 Tap at CYCCNT bit 24
0b10 Tap at CYCCNT bit 26
0b11 Tap at CYCCNT bit 28
Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10].
CYCTAP = 0 selects bit [6] to tap, and CYCTAP = 1 selects bit [10] to tap. When the
selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the
POSTCNT (bits [8:5]) post-scalar counter. That counter will count-down. On a bit change
when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
Advertisement
Table of Contents
