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Instruction Timing
17-6
as due to accesses to slower memory. A branch hint is emitted to the code bus, see
section 14.2.1, which allows a slower system to pre-load; this can reduce the
branch target penalty for slower memory, but never less than what is shown here.
2.
Generally, load-store instructions take two cycles for the first access and one cycle
for each additional access.
3.
UMULL/SMULL/UMLAL/SMLAL use early termination depending on the size
of source values. These are interruptible (abandoned/restarted), with worst case
latency of one cycle. MLAL versions take four to seven cycles and MULL
versions take three to five cycles. In both cases, the signed version is one cycle
longer than the unsigned.
4.
DIV timings depend on dividend and divisor. DIV is interruptible
(abandoned/restarted), with worst case latency of one cycle. When dividend and
divisor are similar in size, divide will terminate quickly. Minimum time is for
cases of divisor larger than dividend and divisor of zero. A divisor of zero returns
zero (not a fault), although a debug trap is available to catch this case.
5.
Sleep is one cycle for the instruction plus as many sleep cycles as appropriate.
WFE only uses one cycle when event has been. WFI will normally be more than
one cycle unless an interrupt happens to pend exactly when entering WFI.
6.
ISB takes one cycle (acts as branch). DMB and DSB will take one cycle unless
data is pending in the write buffer or LSU. If an interrupt comes in during a
barrier, it will be abandoned/restarted.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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