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Instruction Timing
Instruction type
Size
Shift operations
32
Miscellaneous
32
Table Branch
16
Multiply
32
Multiply with
32
64-bit result
Load-store
32
addressing
Load-store Single
32
Load-store
32
Multiple
Branches
32
Load-store Special
32
System
32
System
16
17-4
Cycles count
1
1
1
4+P
1 or 2
3
3-7
-
2
1
2
(+P
if PC is destination)
2
1
1+N
(+P
if PC is loaded)
2
1+N
1
1+P
1
1
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 17-1 Instruction timings (continued)
Description
ASR{S}, LSL{S}, LSR{S}, and ROR {S}.
REV, REVH, REVSH, RBIT, CLZ, SXTB, SXTH, UXTB,
and UXTH. Extension instructions same as corresponding
ARM v6 16-bit instructions.
Table branches for switch/case use. These are LDR with
shifts and then branch.
MUL, MLA, and MLS. MUL is one cycle and MLA and
MLS are two cycles.
UMULL, SMULL, UMLAL, and SMLAL. Cycle count
based on input sizes. That is, ABS(inputs) < 64K will early
terminate.
Supports Format PC+/-imm12, Rbase+imm12,
Rbase+/-imm8, and adjusted register including shifts. "T"
variants used when in Privilege mode.
LDR, LDRB, LDRSB, LDRH, LDRSH, STR, STRB, and
STRH, and "T" variants. PLD is a hint, so acts as NOP if
no cache.
STM, LDM, LDRD, STRD, LDC, and STC.
LDREX, STREX, LDREXB, LDREXH, STREXB,
STREXH, CLREX. Will fault if no local monitor (is IMP
DEF). LDREXD and STREXD are not included in this
profile.
B, BL, and B<cond>. No BLX (1) since always changes
state. No BXJ.
MSR(2) and MRS(2) replace MSR/MRS but also do more.
These are used to access the other stacks and also the status
registers.
CPSIE/CPSID 32-bit forms are not supported.
No RFE or SRS.
CPSIE and CPSID are quick versions of MSR(2)
instructions and use the standard Thumb-2 encodings, but
only allow use of "i" and "f" and not "a".
ARM DDI 0337B
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