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ARM DDI 0337B
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Harvard processor architecture enabling simultaneous instruction fetch with data
load/store.
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Three-stage pipeline.
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Single cycle 32-bit multiply.
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Hardware divide.
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Thumb and Debug states.
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Handler and Thread modes.
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Low latency ISR entry and exit.
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Processor state saving and restoration, with no instruction fetch overhead.
Exception vector is fetched from memory in parallel with the state saving,
enabling faster ISR entry.
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Tightly coupled interface to interrupt controller enabling efficient
processing of late-arriving interrupts.
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Tail-chaining of interrupts, enabling back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts.
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Support for late arriving interrupts.
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Interruptible-continued LDM/STM, PUSH/POP.
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ARMv6 style BE8/LE support.
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ARMv6 unaligned.
The processor core is described further in the following sections.
Registers
The processor contains:
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13 general purpose 32-bit registers
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Link Register (LR)
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Program Counter (PC)
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Program Status Register, xPSR
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two banked SP registers.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Introduction
1-7
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