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Debug Port
12.3.3
Overview of protocol operation
12-22
Idle and reset
Between transfers, the host must either drive the line low to the IDLE state, or continue
immediately with the start bit of a new transfer. The host is also free to leave the line
HIGH, either driven or tristated, after a packet. This reduces the static current drain, but
if this approach is used with a free running clock, a minimum of 50 clock cycles must
be used, followed by a READ-ID as a new re-connection sequence.
There is no explicit reset signal for the protocol. A reset is detected by either host or
target when the expected protocol is not observed. It is important that both ends of the
link become reset before the protocol can be restarted with a training sequence.
Re-synchronization following the detection of protocol errors or after reset is achieved
by providing 50 clock cycles with the wire HIGH, or tristate, followed by a read ID
request. If the SW-DP detects that it has lost synchronization, for example no stop bit is
seen when expected, it leaves the line undriven and waits for the host to either re-try
with a new header, or signals a reset by not driving the line itself. If the SW-DP detects
two bad data sequences in a row, it locks out until a reset sequence of 50 clock cycles
with DBGDI high is seen.
If the host does not see an expected response from SW-DP, it must allow time for
SW-DP to return a data payload. The host can then retry with a read to the SW-DP ID
code register. If this is unsuccessful, the host must attempt a reset.
This section gives an overview of the bi-directional operation of the protocol. It
illustrates each of the possible sequences of operations on the SW-DP interface data
connection.
The sequences of operations illustrated here are:
•
Successful write operation (OK response) on page 12-24
•
Successful read operation (OK response) on page 12-25
•
WAIT response to Read or Write operation request on page 12-25
•
FAULT response to Read or Write operation request on page 12-26
•
Protocol error sequence on page 12-27.
The terms used in the illustrations are described in Key to illustrations of operations.
Key to illustrations of operations
The illustrations of the different possible operations use the following terms:
Start
A single start bit, with value 1.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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