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Field
Name
[9]
-
[8]
MONITORACT
[7]
SVCALLACT
[6:4]
-
[3]
USGFAULTACT
[2]
-
[1]
BUSFAULTACT
[0]
MEMFAULTACT
ARM DDI 0337B
Table 8-20 System Handler Control and State Register bit assignment (continued)
Definition
Reserved
Reads as 1 if the Monitor is active.
Reads as 1 if SVCall is active.
Reserved
Reads as 1 if UsageFault is active.
Reserved
Reads as 1 if BusFault is active.
Reads as 1 if MemManage is active.
The active bits indicate if any of the system handlers are active, running now or stacked
because of pre-emption. This information is used for debugging and is also used by the
application handlers. The pend bits are only set when a fault that cannot be retried has
been deferred because of late arrival of a higher priority interrupt.
Caution
The active bits can be written, cleared or set, but this must be used with extreme caution.
Clearing and setting these does not repair stack contents nor clean up other data
structures. Clearing and setting is intended to be used by context switchers to save a
thread's context, even when in a fault handler. The most common case is to save the
context of a thread which is in an SVCall handler or UsageFault handler, for undefined
instruction and Coprocessor emulation. The model for doing this is to save the current
state, switch out the stack containing the handler's context, load the state of the new
thread, switch in the new thread's stacks, and then return to the thread. The active bit of
the current handler must never be cleared, because the IPSR is not changed to reflect
this. It must only be used to change stacked active handlers.
As indicated, the SVCALLPENDED and BUSFAULTPENDED bits are set when the
corresponding handler is held off by a late arriving interrupt. These bits are not cleared
until the underlying handler is actually invoked. That is, if a stack error or vector read
error occurs before the SVCall or BusFault handler is started, the bits are not cleared.
This enables the push-error or vector-read-error handler to choose to clear them or retry
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Nested Vectored Interrupt Controller
8-29
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