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Nested Vectored Interrupt Controller
Field
Name
[23]
ISRPREEMPT
[22]
ISRPENDING
[21:12]
VECTPENDING
[10]
-
[11]
RETTOBASE
[9:0]
VECTACTIVE
8-20
Table 8-14 Interrupt Control State Register bit assignments (continued)
Type
Definition
Read-only
Must only be used at debug time. It indicates that a pending interrupt is
going to become active in the next running cycle. If C_MASKINTS is
clear in the Debug Halting Control and Status Register, the interrupt is
serviced.
Read-only
Interrupt pending flag. Excludes NMI and Faults:
1 = Interrupt pending
0 = Interrupt not pending.
Read-only
Pending ISR number field. VECTPENDING contains the interrupt
number of the highest priority pending ISR.
-
Reserved.
Read-only
This bit is 1when a return-from-exception would return to Base level of
activation, if no other exception is pending. If in Thread state, in a Handler
more than one level of activation from Base, or in a Handler which is not
marked as active (faults on return), this is 0.
Read-only
Active ISR number field. VECTACTIVE contains the interrupt number of
the currently running ISR, including NMI and Hard Fault. A shared
handler can use VECTACTIVE to determine which interrupt invoked it.
You can subtract 16 from the VECTACTIVE field to index into the
Interrupt Clear/Set Enable, Interrupt Clear Pending/SetPending and
Interrupt Priority Registers. INTISR[0] has vector number 16.
Reset clears the VECTACTIVE field.
Vector Table Offset Register
Use the Vector Table Offset Register to determine:
•
if the vector table is in RAM or code memory
•
the vector table offset.
The register address, access type, and Reset state are:
Address
0xE000ED08
Access
Read/write
Reset state
0x00000000
Figure 8-9 on page 8-21 shows the fields of the Vector Table Offset Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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